Autonomous Traffic Signal Control using Decision Tree

The objective of this paper is to introduce an effective and efficient way of traffic signal light control to optimize the traffic signal duration across each lanes and thereby, to minimize or completely eliminate traffic congestion. This paper introduces a new approach to resolve the traffic congestion problem at junctions by making use of decision trees. The vehicle count in the real time traffic video is determined by Image Processing technique. This information is fed to the decision tree based on which the decision is made regarding the status of traffic signal lights of each lane at the junction at any given instant of time

Performance Analysis of Mesh-based NoC’s on Routing Algorithms

The advent of System-on-Chip (SoCs), has brought about a need to increase the scale of multi-core chip networks. Bus Based communications have proved to be limited in terms of performance and ease of scalability, the solution to both bus – based and Point-to-Point (P2P) communication systems is to use a communication infrastructure called Network-on-Chip (NoC). Performance of NoC depends on various factors such as network topology, routing strategy and switching technique and traffic patterns. In this paper, we have taken the initiative to compile together a comparative analysis of different Network on Chip infrastructures based on the classification of routing algorithm, switching technique, and traffic patterns. The goal is to show how varied combinations of the three factors perform differently based on the size of the mesh network, using NOXIM, an open source SystemC Simulator of mesh-based NoC. The analysis has shown tenable evidence highlighting the novelty of XY routing algorithm

Process-Induced Variability Modeling of Subthreshold Leakage Power considering Device Stacking

The dominance of leakage currents in circuit design has been impelled by steady downscaling of MOSFET into nanometer regime, and has become a significant component of total IC power dissipation. The issue is further aggravated with the inability to gauge the tolerance of process parameters around their nominal value. Consequently, the drive to improve the static power prediction has enticed accurate and reliable modeling of leakage current, specifically for ultralow power applications. In contrast to gate- and band-to-band-tunneling leakages, subthreshold leakage exhibits high susceptibility to process variations and hence has been considered for variability modeling. Fluctuations in the device electrical and geometry parameters result in a wider distribution of subthreshold leakage current. Hence, taking into account stacking effect, an analytical variability model to estimate subthreshold leakage power in subthreshold circuits, in the presence of threshold voltage variations is proposed. Further, the impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model-generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700× computationally faster than SPICE simulations with mean error being less than 0.19%. In this paper, an analytical variability model to estimate subthreshold leakage power in the presence of threshold voltage variations is proposed. The impact of threshold voltage variability on subthreshold leakage power is modeled in conjunction with simultaneous variations in gate length and width. The leakage power variability is characterized by model-generated distributions obtained using Monte Carlo analysis and validated against SPICE simulations. The proposed model is about 700× computationally faster than SPICE simulations with mean error being less than 0.19%